1. Field of the Invention
The present invention relates to an improved method of making a chip device, and more particularly, an improved method of packaging a plurality of DMOS devices and an arrangement for making a plurality of DMOS devices.
2. Description of the Prior Art
Semiconductor power switching devices, and particularly, power MOSFET devices continue to push the lower limits of on-state resistance. While silicon process technology has advanced significantly in the past decade, essentially the same decades old package technology continues as the primary packaging means. Epoxy or soldered die attach along with aluminum or gold wire interconnects is still a preferred power device package methodology.
Recently, chip devices have been manufactured and packaged by connecting the chip within the device to the leads directly through a low resistance solder connection. By using a second leadframe element and solder to connect the device conductors and the first leadframe, a direct connection is enabled. Furthermore, the size and shape of the second leadframe may be tailored to fit the chip device and to minimize its electrical and thermal resistance.
Thus, it is desirable to provide a method and arrangement for making such xe2x80x9cwirelessxe2x80x9d packaging of chip devices manufacturable in a high volume production environment.
In accordance with one aspect of the present invention, a method of making a plurality of DMOS devices includes providing a plurality of bottom leadframes coupled to one another with a pair of rails, attaching a corresponding bumped die including a plurality of solder bumps thereon including a source and gate array to each bottom leadframe, and placing a plurality of top leadframes on the bumped dies such that each top leadframe contacts solder bumps on a corresponding bumped die, the plurality of top leadframes being coupled to one another with a pair of rails.
In accordance with another aspect of the present invention, the method further includes placing a molded body around each top and bottom leadframe with a corresponding bumped die therebetween.
In accordance with another aspect of the present invention, the method includes spot welding a rail at the bottom leadframe and a rail of the top leadframe together.
In accordance with a further aspect of the present invention, the method includes pressfitting a rail on the bottom leadframe and a rail on the top leadframe together.
In accordance with yet another aspect of the present invention, the bumped die is attached to the bottom leadframe with an adhesive wherein the adhesive is cured sometime during the method after the bumped die is attached thereto.
In accordance with a further aspect of the present invention, a plurality of DMOS devices includes a plurality of bottom leadframes that each contain a plurality of leads, a plurality of bumped dies, each bumped die being on a corresponding bottom leadframe and including a source and gate array, and a plurality of top leadframes, each top leadframe being coupled to a corresponding bumped die and including a plurality of leads. The plurality of DMOS devices further includes four rails, a first rail being connected to a first side of each of the top leadframes, a second rail being connected to a second side of each of the top leadframes, a third rail being connected to a first side of each of the bottom leadframes, and a fourth rail being connected to a second side of each of the bottom leadframes. The bottom leadframe has leads coupled to drain terminals on the bumped die, the top leadframe has a lead coupled to a gate terminal on the bumped die, and leads coupled to source terminals on the bumped die, and the first rail is coupled to the third rail while the second rail is coupled to the fourth rail.
Thus, the present invention provides a method for packaging xe2x80x9cwirelessxe2x80x9d chip devices in a high volume production environment. The method provides improved heat dissipation, excellent lead co-planarity control, low lead stress trim and form process, no loose metals at the trim and form process, unidirectional mold gating for better cavity fill and less compound flow turbulence, better manufacturability, and a flexible bumped die attach process.
Other features and advantages of the present invention will be understood upon reading and understanding the detailed description of the preferred exemplary embodiments, found hereinbelow in conjunction with reference to the drawings in which like numerals represent like elements.